1. Field of the Invention
Embodiments of the present invention relate to a power converter control device, as well as driving a semiconductor element configuring a power converter, that includes the function of protecting the semiconductor element.
2. Discussion of the Background
Recently, attention has been drawn to an intelligent power module (IPM). The intelligent power module is such that protection circuits for protection against anomalies, such as an overcurrent of each semiconductor element, a voltage drop of a control power source, and overheating, are modularized as one electronic component together with a plurality of semiconductor elements formed of, for example, power transistors, such as IGBTs, and with drive circuits which drive the respective semiconductor elements. Also, it is also proposed in, for example, JP-A-2012-143125 (PTL 1) that in addition to the heretofore described plurality of protection circuits which detect the respective anomalies, a notification circuit, which externally outputs an alarm signal with a preset pulse width in response to the type of the anomaly detected by each protection circuit, is mounted in the intelligent power module.
FIG. 8 is a block diagram showing an outline configuration of this kind of power converter control device. The power converter control device 1 includes an inverter 2 which converts direct current power to alternating current power. A plurality of semiconductor elements configuring the inverter 2, in this example, six IGBTs (Insulated Gate Bipolar Transistors) 11 to 16 are individually driven by drive circuits 3U to 3Z, respectively. Reference numerals 21 to 26 in FIG. 8 denote free wheeling diodes connected in reverse parallel, one between the emitter and collector of each respective IGBT 11 to 16.
The six IGBTs 11 to 16 configuring the inverter 2, by being connected in series by twos, configure three sets of half bridge circuits. The half bridge circuits are interposed between a positive terminal P and negative terminal N connected to an unshown direct current power supply. The three sets of half bridge circuits provided in parallel configure a three-phase full bridge circuit which converts direct current power, supplied between the positive terminal P and the negative terminal N, to three-phase alternating current power. The three-phase alternating current power converted by the inverter 2 is supplied to an alternating current load 4 such as an electric motor.
More particularly, the IGBTs 11, 12, and 13, of the six IGBTs 11 to 16 configuring the inverter 2, which are connected to the positive terminal P side, configure upper arms which generate respective positive U-phase, V-phase, and W-phase powers of three-phase alternating current. Also, the IGBTs 14, 15, and 16 connected to the negative terminal N side configure lower arms which generate respective negative X-phase, Y-phase, and Z-phase powers of three-phase alternating current. The IGBTs 11 to 16 switch the direct current power by being on/off driven in mutually different phases by the drive circuits 3U to 3Z. Further, the IGBTs 11 to 16 output the three phase alternating current powers from the series connection points of th IGBTs 11 to 16 via output terminals U, V, and W.
Also, each of the drive circuits 3U to 3Z, as FIG. 9 shows an outline configuration of the drive circuit 3X as a representative drive circuit, includes a gate control circuit 31 which inputs a control signal Sm given from an unshown inverter control section and on/off controls the gate of the IGBT 14. The control signal Sm is formed of pulse signals which are pulse width modulated (PWMed) in the inverter control section under phase controls responding to the respective U- to Z-phases.
A protection signal (drive stop signal) Sp is input into the gate control circuit 31 from a protection signal generation circuit 35 to be described hereafter. When the protection signal Sp is off (at an H level), the gate control circuit 31 applies the control signal Sm to the gate of the IGBT 14 and on/off drives the IGBT 14. Also, when the protection signal Sp is on (at an L level), the gate control circuit 31 prevents the control signal Sm from passing. The drive of the IGBT 14 is inhibited by the prevention of the control signal Sm from passing, thereby protecting the IGBT 14 against an anomaly.
Also, the drive circuit 3X includes a control voltage detection circuit 32, a current detection circuit 33, and a temperature detection circuit 34 as the plurality of protection circuits which realize the function of protecting the IGBT 14. The control voltage detection circuit 32 includes a first comparator CP1 which compares a control voltage Vcc of the drive circuit 3U supplied from an external power supply and a preset first threshold voltage Vth1. When the control voltage Vcc drops to and below the first threshold voltage Vth1, the control voltage detection circuit 32 formed of the first comparator CP1 detects this drop as an anomalous drop of the control voltage Vcc and outputs an H-level voltage anomaly detection signal Svd.
Also, the current detection circuit 33 includes a second comparator CP2 which compares a voltage Vi indicating a current I, flowing through the IGBT 14, which is detected from the current detection emitter of the IGBT 14 and a preset second threshold voltage Vth2. When the voltage Vi exceeds the second threshold voltage Vth2, the current detection circuit 33 formed of the second comparator CP2 detects this excess as an overcurrent and outputs an H-level overcurrent anomaly detection signal Soc.
Furthermore, the temperature detection circuit 34 includes a third comparator CP3 which compares a voltage Vt indicating a temperature T of the IGBT 14 detected by a temperature detection diode 18 acting as a temperature sensor mounted in a semiconductor chip which is the same as the IGBT 14, specifically, the temperature T of the semiconductor chip in which the IGBT 14 is formed, and a preset third threshold voltage Vth3. When the voltage Vt drops below the third threshold voltage Vth3, the temperature detection circuit 34 formed of the third comparator CP3 detects this drop as overheat and outputs an H-level overheat anomaly detection signal Soh.
When one of the detection circuits 32, 33, and 34 outputs its respective anomaly detection signal Svd, Soc, and Soh, the protection signal generation circuit 35 is biased via an OR circuit 36 to generate the protection signal Sp of the L level over a fixed time and gives the protection signal Sp of the L level to the gate control circuit 31. Also, the protection signal Sp of the L level is also given to the other drive circuits 3Y and 3Z via a terminal AE. By so doing, not only the drive of the IGBT 14, but also the drives of the remaining IGBTs 15 and 16 are inhibited by the protection signal Sp of the L level.
The anomaly detection signals Svd, Soc, and Soh output by the detection circuits 32, 33, and 34, respectively, are given to an alarm signal generation circuit 37. The alarm signal generation circuit 37 generates alarm signals when given the anomaly detection signals Svd, Soc, and Soh from the detection circuits 32, 33, and 34. The alarm signals are formed one of each of pulse signal trains, with mutually different pulse widths Tvd, Toc, and Toh, in each of which the pulse signals string with a predetermined pulse interval Ta spaced from one another and which are correlated in advance to the respective detection circuits 32, 33, and 34, as shown in, for example, FIGS. 10A, 10B, and 10C, respectively. Incidentally, the respective pulse widths Tvd, Toc, and Toh of the pulse signal trains forming the alarm signals are set to be, for example, Tvd (=T), Toc (=2T), and Toh (=4T). Further, the alarm signals formed of the pulse signal trains are externally output via an output transistor 38, thus contributing to generation of the control signal Sm. The control signal Sm is given to the inverter control section and used to drive the drive circuit 3X.
In recent years, from the viewpoint of energy management, there is a mounting demand for wanting to constantly monitor the temperatures of the IGBTs 11 to 16 which are semiconductor elements in the intelligent power module (IPM). However, the number of output terminals increases in the IPM in order to individually detect and externally output the temperatures of a plurality of semiconductor elements. Furthermore, there arises a problem that a processing burden in the inverter control section increases. As a technique to solve this kind of problem, it is proposed in, for example, JP-A-2000-134074 (PTL 2) to individually detect the temperatures of the plurality of semiconductor elements and select and externally output highest temperature information of these items of temperature information.
However, according to the technique introduced in PTL 2, it is necessary to collect items of temperature information, detected by a plurality of temperature sensors, via an analogue insulation amplifier. Moreover, as analogue voltages indicating the items of temperature information are externally output, the configuration of a processing circuit therefor is complicated, thus undeniably triggering a cost increase. Furthermore, it is necessary to provide dedicated output terminals, specifically, analogue ports for externally outputting the items of temperature information in addition to output terminals, specifically, digital ports from which to externally output the alarm signals. Hence, it is undeniable that the number of output terminals of the semiconductor module (IPM) increases.